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说明：具有 SGMII 接口、支持工作温度范围的耐用型低延迟千兆位以太网 PHY 收发器 48-VQFN -40 to 105

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说明：The KSZ8842-series of 2-port switches includes PCI and non-PCI CPU interfaces.The datasheet describes the KSZ8842-PMQL/PMBL PCI CPU interface chips. KSZ8842-PMQL is PQFP package chip, KSZ8842-PMBL is LFBGA package chip. For information on the KSZ8842-MQL/MBL CPU non-PCI interface switches, refer to the KSZ8842-MQL/MBL datasheet.The KSZ8842-PMQL/PMBL is the industry's first fully managed 2-port switch with a 32-bit/33MHz PCI processor interface. It is a proven, 4th generation, integrated Layer 2 switch that

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说明：Microchip's LAN7431 is a PCIe 3.1 (at 2.5GT/s) to Reduced Gigabit Media Independent Interface (RGMII)?Gigabit Networking bridge providing an ultra-high-performance and cost-effective PCIe to Ethernet connectivity solution.? LAN7431 contains an integrated RGMII interface, PCIe PHY, PCIe endpoint controller, 10/100/1000 Gigabit Ethernet MAC, Integrated OTP, JTAG TAP and EEPROM controller.PCIe-based networking provides flexibility for the routing and placement of network connections anywhere in the system

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说明：The KSZ8851 is a single-port controller chip with a SPI or 8-/16-/32-bit non-PCI CPU interface.Available in 32-/48-/128-pin packages, the KSZ8851 is for applications requiring cost-effective, high-throughput Ethernet connectivity in traditional embedded systems with MCUs or MPUs.KSZ8851SNL/SNLI: SPI interface, 32-pin packageKSZ8851-16MLL: 8-/16-bit host bus, 48-pin packageKSZ8851-16/32MQL: 16-/32-bit host bus, 48-pin package (-16MQL) or 128-pin package (-32MQL)The KSZ8851 is a single chip, mixed analog/digi

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供应商：自营(DL0001)

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说明：1.2Gb 至 1.6Gb 以太网收发器 64-HVQFP -40 to 85

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供应商：自营(DL0001)

说明：The KSZ9896 is a fully integrated layer 2, managed, six-port gigabit Ethernet switch with numerous advanced features. Five of the six ports incorporate 10/100/1000 Mbps PHYs. The sixth port has a MAC interface that can be configured as GMII, RGMII, MII or RMII.Full register access is available by SPI or I2C interfaces, and by optional in-band management via any of the data ports. PHY register access is provided by a MIIM interface.Security features include support for IEEE 802.1X port-based authenticat