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说明：The 74LVC573A provides eight transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance stat

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说明：The MC74HCT259A is identical in pinout to the LS259. The device inputs are compatible with standard CMOS and LSTTL outputs. The HCT259A has four modes of operation as shown in the mode selection table. In the addressable latch mode, the data on Data In is written into the addressed latch. The addressed latch follows the data input with all nonaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous state and are unaffected by the Data or Address inputs.

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说明：The MIC58P01 parallel-input latched driver is a high-voltage (80V), high-current (500mA) integrated circuit comprised of eight CMOS data latches, a bipolar Darlington transistor driver for each latch, and CMOS control circuitry for the common CLEAR, STROBE, and OUTPUT ENABLE functions. Similar to the MIC5801, additional protection circuitry supplied on this device includes thermal shutdown, under voltage lockout (UVLO), and overcurrent shutdown. The bipolar/CMOS combination provides an extremely low-power

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说明：汽车类具有三态输出的八路透明 D 类锁存器 20-TSSOP -40 to 125

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说明：具有三态输出的高速 CMOS 逻辑八路反向透明锁存器 20-PDIP -55 to 125

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说明：具有三态输出的 3.3V ABT 八路透明 D 类锁存器 20-VQFN -40 to 85

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说明：具有三态输出的 3.3V ABT 八路透明 D 类锁存器 20-SO -40 to 85

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说明：具有三态输出的 16 位透明 D 类锁存器 48-TSSOP -40 to 85

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